Digital systems of the type used in computer applications frequently include frequency dividers in the form of various types of digital counters. Prior designs typically use either reloadable binary counters, Johnson counters (for short counts) , or shift counters with fixed state counts. All of these circuits provide fast, modular-N counters for programmable frequency divisions. Where the frequency division is fixed, the classic approach is t0 use a shift counter of N stages, with an exclusive OR (XOR) gate feedback from the last stages to produce a repeating sequence of a predetermined count length (division ratio) of 2.sup.n -1.
Of the various types of counters, shift registers constitute the fastest possible state logic. Thus, implementation of frequency dividers by means of shift register logic is preferred, where high speed operation is desired.
Another objective is to combine the high speed with power efficiency; so that the frequency division device or counter can be used in the feedback path of high speed frequency synthesis phase-lock loops (PLLs), for example. This combined need for high speed at low power dictates extreme circuit simplicity and minimum gate widths for the programmable counters. In prior art shift register counters, the exclusive OR (XOR) feedback path requires a gate arrangement which consumes a substantial amount of chip real estate and imposes speed limitations on the system operation.
Shift register counters typically also include a set of terminal count logic gates for producing an output when the desired count length has been reached. The output of these terminal count logic gates then may be used to pre-load the register to initiate a new count cycle. For a properly operating system, the terminal count logic theoretically is all that is required. Situations, however, do arise where a "trap state" of the counter may occur. This is a state when all stages of the counter are filled with "zero" and no terminal count can be reached. In such a situation, the counter remains in the trapped state and fails to operate. To prevent such a system failure from occurring, a second logic gate set is coupled to the stages of the counter to operate as a trap detector for detecting the situation where the "trap" state of the counter arises.
Normally, no output ever should be obtained from a trap detector, since the situation which produces such an output should not ever occur. If the trap detector, however, does detect a "trap state", the output of the trap detector is used to apply a signal to the pre-load inputs of the counter or to any stage of the counter to clear the trap state. This then removes the "trap" state situation. Under normal conditions of operation, the trap detector logic is never actuated. This logic, however, does impose an additional loading of the counter outputs, since the outputs of the counter are coupled to two different sets of logic, namely the terminal count logic and the trap detect logic.
It is desirable to combine the terminal count detection and trap detection for a shift counter to improve the simplicity of design and maximize the speed of operation of a shift counter.